1. Field of the Invention
The present invention relates in general to equipment for automatically testing electronic circuits and in particular to a test head structure for holding components of a per-pin integrated circuit tester.
2. Description of Related Art
An integrated circuit tester applies patterns of logic signals to input terminals of an integrated circuit (IC) and acquires the resulting logic signal patterns produced at its output terminals. Testers typically include a separate "pin electronics" circuit for each IC terminal. During each cycle of a test, a pin electronics circuit can, for example, send a high or low logic level test signal to the pin, sample an IC output signal at the pin and store data indicating its logic level, or do nothing. The action each pin electronics circuit takes during a given test cycle is controlled by the value of input data (a "test vector") supplied thereto at the start of the cycle. A test vector may also include timing data that tells the pin electronics circuit when to carry out the action during the test cycle.
Early IC testers employed a central addressable memory storing a large word at each address, each word being formed by all of the vector data needed for every pin electronics circuit for a particular test cycle. Thus, for example, if an IC had 8 terminals and a tester employed 8-bit vector data words, a 64-bit word was stored at each vector memory address. The vector memory was sequentially addressed so that it read out a next word during each test cycle. The eight vectors contained in the read out word were concurrently distributed to the pin electronics circuits by a large star bus. Thus a vector memory for a test spanning one million test cycles stored one million 64-bit words at successive addresses.
As the size and complexity of IC's increased, so too did the number of terminals on an IC; some IC's now have hundreds of pins. Due to the large number of parallel buses needed to transmit the vectors concurrently to the pin electronics, the use of a centralized vector memory has become impractical. U.S. Pat. No. 4,862,067 issued Aug. 29, 1989 to Brune et al describes a "per pin" integrated circuit tester in which vector storage memory is distributed to the tester nodes. Brune's tester includes a central address generator and a set of tester nodes, one node for each terminal of a device under test (DUT). Each node includes a vector memory for storing a sequence of test vectors, one for each cycle of the test. During a test the central address generator successively increments the address of the test vector memories of all nodes prior to the start of each test cycle so that each test vector memory reads out a new test vector and delivers it to the node's pin electronics at the beginning of each test cycle. In Brune's IC tester, all vector memories are linked to the host computer via a common bus through which the host computer loads vectors into the vector memories before the test. Thus the prior art multiplicity of vector buses leading from a central vector memory to all tester nodes is replaced by a single computer bus linking a host computer to distributed vector memories. While Brune's system reduces the amount of wiring in a tester, it increases the time required to program the tester. Since each vector memory must store one vector for each cycle of the test, the number of vectors that must be distributed to the vector memories can be so enormous that band width limitations on the computer bus greatly limit the speed with which an IC tester can be programmed for a test.
A tester system may reduce the amount of data that must be distributed to the tester nodes by distributing algorithmic instructions for generating vectors instead of the vectors themselves. In such a system, each node includes an instruction processor for generating the vectors during the test based on the locally stored instructions. Integrated circuit testers typically carry out repetitive patterns of actions at various IC terminals at various times during a test. Thus a set of instructions for generating a sequence of vectors including repeating patterns may require less storage space than the sequence of vectors itself. U.S. Pat. No. 4,994,732 issued Feb. 19, 1991 to Jeffery et al describes a per-pin tester which distributes some instruction processing capability to the nodes. In Jeffery's tester, only the first instance of a vector pattern is stored in the vector memory along with a loop instruction indicating the length of the pattern and the number of times a pattern is to be repeated. Each node of a tester includes an instruction processor which sequentially reads vectors out of the vector memory and supplies them to the pin electronics during successive test cycles. When the vector memory controller encounters a loop instruction, it repeats the pattern the indicated number of times. Thus the number of vectors needed to be sent to and stored in a vector memory before a test is reduced.
Signal delay becomes problematic when we employ distributed instruction processors in a large circuit tester. Signal delay is critical when testing an integrated circuit because test activities at all nodes must be precisely coordinated. For example, a test signal sent to an IC input terminal may engender a response in an IC output signal at an IC output terminal. A tester should be able to measure the output signal response at the output terminal at the end of a precisely timed interval following application the test signal to the input terminal. As we increase the complexity of the tester nodes, we also increase the physical size of the nodes and it becomes more difficult to keep all nodes close to the device under test. As the distance between an IC terminal and the tester node that services it increases, so too does the amount of time required for a test or response signal to travel between the IC terminal and the tester node. When testing high speed integrated circuits, this signal travel time becomes a significant portion of the apparent IC response time, thereby complicating tester programming and interpretation of test results.
U.S. Pat. No. 4,517,512 issued May 14, 1985 to Petrich et al describes a test head which holds pin electronics close to the device under tests. In Petrich's test head, a set of circuit cards each containing pin electronics for four IC pins, are arrayed in a radial pattern about a vertical axis of a carrier board. The integrated circuit DUT is mounted on an interface board resting on top of the circular array of pin electronics cards. Test signal input/output terminals at the upper edges of the pin electronics cards connect to the interface board. The interface board delivers test signals from the pin electronics card input/output terminals to the device under test. Petrich's test head is designed to position the pin electronics cards close to the DUT so as to minimize distances between the pin electronics cards and the DUT.
Heat also becomes problematic when we attempt to closely pack distributed instruction processors in a large circuit tester. In Petrich's test head, a duct carries cooling air from a blower to an aperture in the center of the carrier board. The air passes over the pin electronics cards and carries the heat away.
While Petrich's test head brings the pin electronics close to the DUT and keeps the pin electronics cool, the number of pin electronics cards it can accommodate is limited by the allowable diameter of the circular array of pin electronics cards. To increase the number of pin electronics cards, it is necessary to increase the diameter of the circular array, thereby increasing the test signal path distance between the cards and the DUT. One could also increase density by placing pin electronics servicing more than four pins on each pin electronics card. However when pin electronics for only one IC terminal becomes defective, the entire pin electronics card must be replaced, thereby increasing repair costs. Also Petrich's test head does not provide easy access to the pin cards for maintenance and replacement. Finally, when the blower forces air into the test head, that air passes through the head where it is heated and then exits into the room containing the test head. The hot air emanating from the test head can be uncomfortable to operators and maintenance personnel in the vicinity of the test head.
What is needed is a test head structure for holding large numbers of nodes of a per-pin integrated circuit tester close to a device under test while keeping the nodes cool. The test head should provide ready access to pin electronics for maintenance, should cool the nodes without heating the area around the test head, and should require minimal amounts of cabling. The test head should also be highly modular so that system can be sized for the IC being tested and easily expanded.